The present invention relates to improved semiconductor imaging devices and, in particular, to CMOS imagers with improved color separation and sensitivity.
The semiconductor industry currently uses different types of semiconductor-based imagers, such as charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays, among others.
CCD technology is often used for image acquisition and has a number of advantages which makes it the preferred technology, particularly for small size imaging applications. CCDs are capable of large formats with small pixel size and they employ low noise charge domain processing techniques. CCD imagers suffer, however, from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read-out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. In addition, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. Further, CCDs may suffer from incomplete charge transfer from pixel to pixel which results in image smear.
Because of the inherent limitations in CCD technology, CMOS imagers have been increasingly used as low cost imaging devices. A filly compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.
CMOS imagers have several advantages over CCD imagers, such as, for example, low voltage operation and low power consumption, compatibility with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion), random access to the image data, and lower fabrication costs. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate, photoconductor or a photodiode overlying a doped region of a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate, photoconductor or photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the charge accumulation region of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout.
A schematic view of an exemplary CMOS imaging circuit is illustrated in FIG. 1. As it will be described below, the CMOS imaging circuit includes a photogate for accumulating photo-generated charge in an underlying portion of the substrate. It should be understood, however, that the CMOS imager may include a photodiode or other image to charge converting device, in lieu of a photogate, as the initial accumulator for photo-generated charge.
FIG. 1 shows a simplified photodetector circuit for a pixel cell 14 of an exemplary CMOS imager using a photogate and and a readout circuit 60. It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, in practical use there will be an Mxc3x97N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The pixel cell 14 is shown in part as a cross-sectional view of a semiconductor substrate 16, which is typically a p-type silicon, having a surface well of p-type material 20. An optional layer 18 of p-type material may be used, if desired. Substrate 16 may be formed of Si, SiGe, Ge, or GaAs, among others. Typically, the entire semiconductor substrate 16 is a p-type doped silicon substrate including a surface p-well 20 (with layer 18 omitted), but many other options are possible, such as, for example p on pxe2x88x92 substrates, p on p+ substrates, p-wells in n-type substrates or the like.
An insulating layer 22 of silicon dioxide, for example, is formed on the upper surface of p-well 20. The p-type layer may be a p-well formed in substrate 16. A photogate 24, thin enough to pass radiant energy or of a material which passes radiant energy, is formed on the insulating layer 22. The photogate 24 receives an applied control signal PG which causes the initial accumulation of pixel charges in n+ region 26. An n+ type region 26, adjacent to one side of the photogate 24, is formed in the upper surface of p-well 20. A transfer gate 28 is formed on insulating layer 22 between the n+ type region 26 and a second n+ type region 30 formed in p-well 20. The n+regions 26 and 30 and transfer gate 28 form a charge transfer transistor 29 which is controlled by a transfer signal TX. The n+ region 30 is typically called a floating diffusion region. The n+ region 30 is also a node for passing charge accumulated thereat to the gate of a source follower transistor 36 described below.
A reset gate 32 is also formed on insulating layer 22 adjacent and between the n+ type region 30 and another n+ region 34 which is also formed in p-well 20. The reset gate 32 and n+ regions 30 and 34 form a reset transistor 31 which is controlled by a reset signal RST. The n+ type region 34 is coupled to voltage source VDD, of for example, 5 volts. The transfer and reset transistors 29, 31 are n-channel transistors as described in this implementation of a CMOS imager circuit in a p-well. As known in the art, it is also possible to implement a CMOS imager in an n-well, in which case each of the transistors would be p-channel transistors. It should also be noted that, while FIG. 1 shows the use of a transfer gate 28 and associated transistor 29, this structure provides advantages, but is not required.
Pixel cell 14 also includes two additional n-channel transistors, a source follower transistor 36 and a row select transistor 38. Transistors 36, 38 are coupled in series, source to drain, with the source of transistor 36 also coupled over lead 40 to voltage source VDD and the drain of transistor 38 coupled to a lead 42. The drain of the row select transistor 38 is connected via conductor 42 to the drains of similar row select transistors for other pixels in a given pixel row. A load transistor 39 is also coupled between the drain of transistor 38 and a voltage source VSS, of for example 0 volts. Transistor 39 is kept on by a signal VLN applied to its gate.
The imager includes a readout circuit 60 (FIG. 1) which includes a signal sample and hold (S/H) circuit including a S/H n-channel field effect transistor 62 and a signal storage capacitor 64 connected to the source follower transistor 36 through row transistor 38. The other side of the capacitor 64 is connected to a source voltage VSS. The upper side of the capacitor 64 is also connected to the gate of a p-channel output transistor 66. The drain of the output transistor 66 is connected through a column select transistor 68 to a signal sample output node VOUTS and through a load transistor 70 to the voltage supply VDD. A signal called xe2x80x9csignal sample and holdxe2x80x9d (SHS) briefly turns on the S/H transistor 62 after the charge accumulated beneath the photogate electrode 24 has been transferred to the floating diffusion node 30 and from there to the source follower transistor 36 and through row select transistor 38 to line 42, so that the capacitor 64 stores a voltage representing the amount of charge previously accumulated beneath the photogate electrode 24.
The readout circuit 60 also includes a reset sample and hold (S/H) circuit including a S/H transistor 72 and a signal storage capacitor 74 connected through the S/H transistor 72 and through the row select transistor 38 to the source of the source follower transistor 36. The other side of the capacitor 74 is connected to the source voltage VSS. The upper side of the capacitor 74 is also connected to the gate of a p-channel output transistor 76. The drain of the output transistor 76 is connected through a p-channel column select transistor 78 to a reset sample output node VOUTR and through a load transistor 80 to the supply voltage VDD. A signal called xe2x80x9creset sample and holdxe2x80x9d (SHR) briefly turns on the S/H transistor 72 immediately after the reset signal RST has caused reset transistor 31 to turn on and reset the potential of the floating diffusion node 30, so that the capacitor 74 stores the voltage to which the floating diffusion node 30 has been reset.
The readout circuit 60 provides correlated sampling of the potential of the floating diffusion node 30, first of the reset charge applied to node 30 by the reset transistor 31 and then of the stored charge from the photogate 24. The two samplings of the diffusion node 30 charges produce respective output voltages VOUTR and VOUTS of the readout circuit 60. These voltages are then subtracted (VOUTS-VOUTR) by subtractor 82 to provide an output signal terminal 81 which is an image signal independent of pixel to pixel variations caused by fabrication variations in the reset voltage transistor 31 which might cause pixel to pixel variations in the output signal.
FIG. 2 illustrates a block diagram for a CMOS imager having a pixel array 200 with each pixel cell being constructed in a manner similar to that of pixel cell 14 of FIG. 1. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array 200 are all turned on at the same time by a row select line, such as line 86, and the pixels of each column are selectively output by a column select line, such as line 42. A plurality of rows and column lines are provided for the entire array 200. The row lines are selectively activated by the row driver 210 in response to row address decoder 220 and the column select lines are selectively activated by the column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the control circuit 250 which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 210, 260 which apply driving voltage to the drive transistors of the selected row and column lines.
FIG. 3 shows a simplified timing diagram for the signals used to transfer charge out of pixel cell 14 of the CMOS imager of FIG. 1. The photogate signal PG is nominally set to 5V and pulsed from 5V to 0V during integration. The reset signal RST is nominally set at 2.5V. As illustrated in FIG. 3, the process begins at time t0 by briefly pulsing reset voltage RST to 5V. The RST voltage, which is applied to the gate 32 of the reset transistor 31, causes transistor 31 to turn on and the floating diffusion node 30 to charge to the VDD voltage present at n+ region 34 (less the voltage drop VTH of transistor 31). This resets the floating diffusion node 30 to a predetermined voltage (VDD-VTH). The charge on the floating diffusion node 30 is applied to the gate of the source follower transistor 36 to control the current passing through transistor 38, which has been turned on by a row select (ROW) signal, and load transistor 39. This current is translated into a voltage on line 42 which is next sampled by providing a SHR signal to the S/H transistor 72, which charges capacitor 74 with the source follower transistor output voltage on line 42 representing the reset charge present at floating diffusion node 30. The PG signal is next pulsed to 0 volts, causing charge to be collected in n+ region 26.
A transfer gate voltage TX, similar to the reset pulse RST, is then applied to transfer gate 28 of transistor 29 to cause the charge in n+ region 26 to transfer to floating diffusion node 30. It should be understood that, for the case of a photogate, the transfer gate voltage TX may be pulsed or held to a fixed DC potential. For the implementation of a photodiode with a transfer gate, the transfer gate voltage TX must be pulsed. The new output voltage on line 42 generated by source follower transistor 36 current is then sampled onto capacitor 64 by enabling the sample and hold switch 62 by signal SHS. The column select signal is next applied to transistors 68 and 70 and the respective charges stored in capacitors 64 and 74 are subtracted in subtractor 82 to provide a pixel output signal at terminal 81. It should also be noted that CMOS imagers may dispense with the transfer gate 28 and associated transistor 29, or retain these structures while biasing the transfer transistor 29 to an always xe2x80x9conxe2x80x9d state.
For black and white imaging, each pixel cell 14 (FIG. 1) represents a pixel of light energy. Color imaging, however, requires three pixel cells 14 for the formation of a single color pixel. For example, a conventional color pixel sensor 50 is illustrated in FIG. 4 as including a red active pixel sensor cell 52, a blue active pixel sensor cell 54 and a green active pixel sensor cell 56, spaced apart on the semiconductor substrate 16 by isolation regions 19. Each of the red, blue and green active pixel sensor cells 52, 54, 56 have respective red, blue and green filters 53, 55, 57, which allow only red, blue and green photons, respectively, to pass through. Thus, the red, blue and green active pixel sensor cells 52, 54, 56 operate in a similar way to the pixel cell 14 (FIG. 1), except that the information provided by each of the red, blue and green active pixel sensor cells 52, 54, 56 is limited by the intensities of the red, blue and green light, respectively.
One of the drawbacks of using a color pixel sensor, such as the color pixel sensor 50 of FIG. 4, is that the minority carriers in the blue active pixel sensor cell 54, for example, are substantially more likely to be lost in recombination than the minority carriers formed in the red and green active pixel sensor cells 52, 56. The difference in the recombination rates is due to the relatively shallow penetration depths of the blue photons, the higher majority carrier concentration that exists in the n+ region 30 than in the substrate 16, and the depth of the junction. For example, even though the average penetration of a blue photon in a CMOS photodiode is approximately 0.2xcexc, a large number of blue photons fail to penetrate beyond the 0.1xcexc junction. This way, a large amount of these photons are lost to recombinations and the blue cell response remains substantially below the red cell and green cell responses.
One technique for equalizing the red, blue and green responses is to increase the amplification provided by the column sense amplifier that corresponds to the blue active pixel sensor cell 54. For example, if the blue response is xe2x80x9cnxe2x80x9d times lower that the red and green responses, equalized red, blue and green responses are obtained if the column sense amplifiers corresponding to the blue active pixel sensor cell 54 are set to provide a gain of xe2x80x9cnxe2x80x9d times. This technique, however, introduces noise by the charge-to-voltage conversion process, as well as by the sense amplifiers themselves. Thus, along with the blue signal, the noise also increases xe2x80x9cnxe2x80x9d times.
There is needed, therefore, an improved pixel sensor cell for use in an imager that exhibits improved color separation, a better signal-to-noise ratio, and reduced cross talk. A method of fabricating a pixel sensor cell exhibiting these improvements is also needed.
The present invention provides multiple graded doped regions formed below respective pixel sensor cells of a CMOS imager. In an exemplary embodiment, a deep retrograde p-well is formed under a red pixel sensor cell of a semiconductor substrate to increase the red response. A shallow p-well is formed under the blue pixel sensor cell to decrease the red and green responses, while a shallow retrograde p-well is formed below the green pixel sensor cell to increase the green response and decrease the red response. Each of the multiple graded doped regions would have an entire array of respective pixels formed therein, and may also have peripheral circuitry formed therein. If the peripheral circuitry is formed in the multiple graded doped regions, the multiple graded doped regions may have a different dopant profile in the peripheral region than in the array region.
Also provided are methods for forming a color pixel cell having multiple graded doped regions of the present invention.
Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.